1. Technical Field
The present invention relates to memory circuits in general, and in particular to static random access memory circuits. Still more particularly, the present invention relates to an apparatus for hardening a static random access memory cell from single event upsets.
2. Description of the Prior Art
A static random access memory (SRAM) circuit typically includes multiple six-transistor memory cells. In certain environments, such as satellite orbital space, in which the level of radiation is relatively intense, SRAMs are more susceptible to single event upsets (SEUs) or soft errors. Also, as the channel widths of transistors scale below 250 nm range, current six-transistor memory cells employing cross-coupled resistor based isolation do not effectively dampened SEU.
Generally speaking, SEUs are caused by electron-hole pairs created by, and travelling along the path of, a single energetic particle as it passes through SRAM cells. Should the energetic particle generate a critical charge within a storage node of an SRAM cell, the logic state of the SRAM cell will be upset. Thus, the critical charge is the minimum amount of electrical charge required to change the logic state of the SRAM cell.
Smaller transistors result in less drive current to restore the internally discharged node. Available resistor physical design area and gate capacitance are also less, which reduces the RC time constant between cross-coupled nodes within a SRAM cell. Consequently, it would be desirable to provide an improved apparatus for hardening a SRAM cell from SEUs.